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TRF7970A
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Figure 6-23. IRQ After Inventory Command
The IRQ status register read (0x6C) yields 0x80, which indicates that TX is indeed complete. This is
followed by a dummy clock. Then, if a tag is in the field and no error is detected by the reader, a second
interrupt is expected and occurs (in this example) approximately 4 ms after first IRQ is read and cleared.
In the continuation of the example (see Figure 6-24 ), the IRQ Status Register is read using method
previously recommended, followed by a single read of the FIFO status register, which indicates that there
are 10 bytes to be read out.
Figure 6-24. Read IRQ Status Register After Inventory Command
This is then followed by a continuous read of the FIFO. The first byte is (and should be) 0x00 for no error.
The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to
the next most significant byte, the MFG code (shown as 0x07 (TI silicon)).
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